1. Field of the Invention
The present invention relates generally to techniques for manufacturing integrated circuits and, in particular, to techniques for characterizing interconnect structures.
2. Description of the Related Art
Increased operating speeds and reduced power consumption of integrated circuits may be achieved by decreasing operating voltages and decreasing critical dimensions (i.e., the size of the smallest geometrical features that can be formed during semiconductor manufacturing using a given process technology). Decreased operating voltages and decreased critical dimensions increase the significance of capacitances associated with metal lines and may result in such capacitances, e.g., those associated with back end-of-line structures (i.e., structures produced by process steps for contacting devices formed on an integrated circuit) dominating circuit speed. Increasing the number of metal layers makes it difficult to measure the realized parameters for individual layers (e.g., metal layers or insulating layers) obtained from a given process. Accordingly, there is a need for a technique that efficiently and effectively quantifies the effects of capacitances, such as those formed by back end-of-line layers on circuit performance.